The Time-Triggered Architecture

Two Novel D-Flip Flops with Level Triggered Reset in Quantum Dot Cellular Automata Technology

Quantum dot cellular automata (QCA) introduces a pioneer technology in nano scale computer architectures. Employing this technology is one of the solutions to decrease the size of circuits and reducing power dissipation. In this paper, two new optimized FlipFlops with reset input are proposed in quantum dot cellular automata technology. In addition, comparison with related works is performed.Th...

High Speed Delay-Locked Loop for Multiple Clock Phase Generation

In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...

Integration of Group Membership with Clock Synchronization in Time-Triggered Architecture (TTA)

Modeling Time-Triggered Architecture Based Real-Time Systems Using SystemC

This paper proposes a SystemC based extension for the modeling of TimeTriggered Architecture (TTA) based real-time embedded systems. The extension called Executable Time-Triggered Model (E-TTM) supports the time-triggered model of computation and provides a time domain deterministic modeling framework based on SystemC. E-TTM can be used from the architectural design phase to support early funct...

Mode Handling in the Time-Triggered Architecture

On the Design of Distributed Time-Triggered Embedded Systems

ion, partitioning and segmentation are supported by the time-triggered architecture and its associated design methodology to construct evolvable embedded systems that can be readily understood and modified.